CSE 2203 – Computer Architecture

“A computer once beat me at chess, but it was no match for me at kick boxing.”
— Emo Philips

CSE 2203 - Computer Architecture

Intro

Rationale

This course aims to provide a strong foundation to understand modern computer system architecture and to apply these insights and principles to future computer designs. The course is structured around the three primary building blocks of general-purpose computing systems: processors, memories, and parallel processing.

Objectives

  • To understand the internal architecture of processors.
  • To analyze and evaluate CPU and memory hierarchy performance
  • To understand the design of a pipelined CPU and cache hierarchy.
  • An understanding of trade-offs in modern CPU design including issues affecting superscalar and dynamically scheduled architectures.

Syllabus

Section – A

Introduction:Information performance measurements, instruction and data access method, operation and operand of computer hardware, representing instruction, addressing styles.

 

Basic Processing Unit:Arithmetic logic unit (ALU) operations, floating point operations, designing ALU, Single Bus Architecture, 3-Bus Architecture, Fetching a word from memory, Control Sequence of an instruction, Implementation of Control Sequence in Hardware, Branch Instructions, Hardwired Control, Micro programmed Control, Microinstructions, Micro routine, Control word.

 

Control Unit: Hardwired and Micro- programmed, Hazards, exceptions.

 

Memory: Memory Hierarchy, Register, cache memory, primary memory, secondary memory, Multiple Level Cache Memory, performance measure for first, second and third level cache memory, virtual memory, page fault, translation look a side buffer

 

Section - B

 

Pipelining: Parallel processing using pipelining, improved performance for pipelining, Various types of Hazards, Data Hazard, Instruction Hazard, Control Hazard, Avoiding data hazard, avoiding instruction hazard, avoiding structural hazard. Instruction queue, branch folding, static and
dynamic branch prediction, superscalar operation, precise and imprecise exception, out of order execution.

 

Input Output Devices: Types of i/o devices, how they connected to computer, interrupt, use of interrupt to control the i/o devices, daisy chain connection, interrupt priority

Reference Books

  • Computer Organization and Design: the Hardware/Software Interface - Textbook by David A Patterson and John L. Hennessy.

  • Computer Organization and Architecture - Book by William Stallings

Contents

Declaration: Various materials are collected from Internet to make these slides. These slides are to help taking the class and can be used as a guideline.
  1. 01 – Introduction (Screencast: Introduction to CA)
  2. 02 – Brief History (Screencast: Brief History)
  3. 03 – Performance (Screencast: Performance-1, Performance-2, Performance-3, Performance-4)
  4. 04_1 – Computer Components and BUS Interconnections (Screencast: Components, Bus Interconnections)
  5. 04_2 – MIPS Datapath (Helpful Links: Link1, Link2, Link3, Link4)
  6. 05 – Instruction Sets and Addressing Modes (Screencast: Instruction Set and Addressing Mode)
  7. 06 – Execution Unit (EU – 4 bit Arithmetic Unit Example, EU – 4 bit Arithmetic Unit Example V2, Screencast: Registers, RCA, CLA, ALU Design, Multiplication)
  8. 07 – Instruction Pipeline (Screencast: Instruction Pipeline Data Hazard Resource Hazard, Branch Hazard)
  9. 08 – Memory (Screencast: Memory, Cache Mapping – 1, Cache Mapping – 2)
  10. 09 – Virtual Memory (Screencast: Virtual Memory)
  11. 10 – I/O Modules (Screencast: I/O Modules, Programmed I/O and Interrupt I/O, Direct Memory Access-DMA)
  12. 11 – Control Unit (Screencast: Control Unit)